1. Field of the Invention
The present invention relates to a frequency modulation apparatus that modulates a frequency based on phase modulation data.
2. Description of the Related Art
FIG. 1 shows an example of a conventional synthesizer. This synthesizer 10 is equipped with a voltage controlled oscillator (hereinafter referred to as “VCO”) 11, a frequency divider 12, a phase comparator 13, a reference oscillator 14, and a loop filter 15.
VCO 11 provides a desired output frequency fo, and supplies this to frequency divider 12. The output of frequency divider 12 is supplied to one input of phase comparator 13, and the other input of phase comparator 13 is supplied from reference oscillator 14. The output of phase comparator 13 is filtered by loop filter 15 to eliminate unwanted noise components.
The output of loop filter 15 is then fed back to the control input of VCO 11, by which means output frequency fo of VCO 11 is adjusted so as to become a division ratio multiple value.of the frequency of the reference oscillator 14. The reference frequency (fr) and the comparative frequency obtained by 1/M frequency division of the VCO output (fo) by a variable frequency divider are input to phase comparator 13. The loop stabilizes in the fr=fo/M state.
Thus, the output frequency (fo) becomes fr·M, and the VCO output frequency can be varied in frequency steps Δf=fr by varying frequency division ratio M.
Another example of a conventional synthesizer is shown in FIG. 2. This synthesizer 20 is equipped with a voltage controlled oscillator (hereinafter referred to as “VCO”) 11, a frequency divider 12, a phase comparator 13, a reference oscillator 14, a loop filter 15, and an accumulator 21.
Accumulator 21 is equipped with an adder 22, a comparator 23, and a feedback logic section 24. Adder 22 adds together numerator data K and an addition feedback value from feedback logic section 24. Comparator 23 compares the output value of adder 22 with the reference value, provides a carry output signal to frequency divider 12, and provides the adder 22 output value to feedback logic section 24 where it is held.
If the frequency division ratio of frequency divider 12 is M, when the contents of accumulator 21 become L or greater, an overflow (OVF) signal is output and the frequency division ratio of frequency divider 12 is made M+1. If accumulator 21 increases its contents by K in one reference cycle, the contents will be αK after α cycles. Here, K is an integer such that α>1, K≧0, and L>K.
When αK≧L, accumulator 21 outputs an overflow signal, makes the frequency divider 12 frequency division ratio M+1, and also makes its contents +K−L and performs incrementing again every cycle.
Accumulator 21 causes overflow K times during an L cycle, frequency divider 12 frequency division ratio M is M+1K times in an L cycle and M the remaining L−K times (see FIG. 4). Thus, the average frequency division ratio per L cycle is M+K/L.
Therefore, in the synthesizer shown in FIG. 2, frequency steps can be made small since the average frequency division ratio is M+K/L. However, a problem with the kind of configuration shown in FIG. 2 is that a high level of spurious emission occurs in the vicinity of the center frequency. This is because frequency division ratio M varies with an L cycle as the fundamental period, and the VCO output signal is modulated since 1/L and integer multiple frequency components appear in the phase comparator output signal. Possible ways of reducing this spurious emission are to vary frequency division ratio M frequently, make the varied low-frequency component lower, and make the high-frequency component higher. The higher the frequency component, the more easily it can be reduced with the loop filter 15 cutoff frequency.
Another example of a conventional synthesizer is shown in FIG. 3 (see Japanese Patent Publication No. HEI 5-502154). This synthesizer 30 has a multi-stage accumulator digital network 31 instead of accumulator 21 in the synthesizer shown in FIG. 2.
Multi-stage accumulator digital network 31 is equipped with a plurality of stages of accumulators 32, a plurality of digital delay networks 33, and an adder 34. In synthesizer 30, multi-stage accumulator digital network 31 processes numerator data containing modulation information, generates a precise carry output signal and provides this to frequency divider 12, and performs frequency division ratio changes precisely. In synthesizer 30 shown in FIG. 3, carry output signals of the second-stage and subsequent accumulators (integration circuits) are input to a differentiation circuit and become 0 when averaged, as a result of which frequency division ratio changes are frequent as shown in FIG. 5.
However, a problem with conventional synthesizer 30 shown in FIG. 3 is that, since it can only process numerator data in the range from 0 or above to less than 1, it cannot be used directly in a frequency modulation apparatus that processes phase modulation data exceeding the range from 0 or above to less than 1.